Within computing systems, an interrupt can be considered a signal that receives the attention of a processor and that is usually generated when input/output (I/O) activity is required. For example, interrupts may be generated when a key on the keyboard is pressed or when the mouse or other pointing device is moved. Other types of interrupts are generated by network controllers, storage devices, video devices, and other kinds of hardware devices.
In a computing system with more than one processor, an interrupt is typically delivered to the processor servicing the lowest priority thread. A thread is a part of a process that may be part of a computer program being executed by a processor. A computer program may have one or more processes, and each process may have one or more threads. The threads may be run independently of one another, or may be dependent on one another. The priorities of the threads dictate how many processor cycles the threads receive to execute the threads. A lower-priority thread, for instance, may receive less processor cycles than a higher-priority thread does, especially where the processor in question is executing a large number of threads.
Delivering interrupts to the processor of a multiple-processor computing system that is currently servicing the lowest priority thread is disadvantageous, however. A processor, for instance, may be servicing a large number of low-priority threads, and therefore may be relatively busy. Requiring this processor to also service interrupts can result in degradation of the overall performance of the computing system, because the processor is required to service the interrupts before continuing with servicing the low-priority threads.
Determining the priorities of threads being executed by the processors of a computing system has typically been determined by a transaction known as an external Task Priority Register (xTPR) Update transaction. Periodically each processor provides information regarding the priorities of its threads via such transactions. In this way, the controller or other interrupt-delivery mechanism is able to monitor which processor is servicing the lowest-priority thread, and thus to which processor interrupts should be delivered. It is noted that the operating system itself controls the priority of a task, by updating a corresponding Task Priority Register (TPR) within the processor. When this register is updated by the operating system, the processor then sends a special transaction on its front side bus (FSB) so that interrupt redirection logic can update its register, the xTPR, to which the TPR within the processor corresponds.
However, some processors do not support the xTPR Update transaction. As a result, such processors may not be able to be used within computing systems that deliver interrupts to the processor servicing the lowest priority thread. Furthermore, some operating systems do not utilize these transactions. For example, some versions of Linux do not use the TPR to set interrupt priority levels, such that interrupt delivery to the processor currently servicing the lowest priority thread cannot be achieved in such an operating system.
For these and other reasons, there is a need for the present invention.